1. Technical Field
The invention relates generally to analog-to-digital convertor (ADC), and more particularly, to successive-approximation-register (SAR) ADC.
2. Related Art
A SAR ADC is a type of ADC that applies the binary search algorithm to analog-to-digital conversion. The SAR ADC's conversion rate is generally controlled by a conversion clock that is provided externally. Within each period of the conversion clock, the SAR ADC must sample an analog input and generate a corresponding digital output bit-by-bit, from the most significant bit (MSB) to the least significant bit (LSB).
In order to function properly, the SAR ADC may additionally require a fast clock with a rate much higher than that of the conversion clock. Alternatively, the SAR ADC may additionally require an unbalanced clock with an unbalanced duty cycle. For example, the unbalanced clock's frequency is the same as that of the conversion clock, but the unbalanced clock's duty cycle may be either 20%, 25%, or 40%. However, the unbalanced clock's duty cycle cannot be fine-tuned adaptively.
Either of these two additional requirements may increase the costs of the SAR ADC and make the SAR ADC less favorable. Furthermore, the fact that the unbalanced clock's duty cycle cannot be fine-tuned adaptively sometimes prohibits the SAR ADC from operating in the optimum condition.